An interrupt is an event that occurs randomly in the flow of continuity. It is just like a call you have when you are busy with some work and depending upon call priority you decide whether to attend or neglect it.
Same thing happens in microcontrollers. 8051 architecture handles 5 interrupt sources, out of which two are internal (Timer Interrupts), two are external and one is a serial interrupt. Each of these interrupts has their interrupt vector address. Highest priority interrupt is the Reset, with vector address 0x0000.
Vector Address: This is the address where controller jumps after the interrupt to serve the ISR (interrupt service routine).
Interrupt | Flag | Interrupt vector address |
---|---|---|
Reset | - | 0000H |
INT0 (Ext. int. 0) | IE0 | 0003H |
Timer 0 | TF0 | 000BH |
INT1 (Ext. int. 1) | IE1 | 0013H |
Timer 1 | TF1 | 001BH |
Serial | TI/RI | 0023H |
Reset
Reset is the highest priority interrupt, upon reset 8051 microcontroller start executing code from 0x0000 address.
Internal interrupt (Timer Interrupt)
8051 has two internal interrupts namely timer0 and timer1. Whenever timer overflows, timer overflow flags (TF0/TF1) are set. Then the microcontroller jumps to their vector address to serve the interrupt. For this, global and timer interrupt should be enabled.
Serial interrupt
8051 has serial communication port and have related serial interrupt flags (TI/RI). When the last bit (stop bit) of a byte is transmitted, TI serial interrupt flag is set and when last bit (stop bit) of receiving data byte is received, RI flag get set.
IE register: Interrupt Enable Register
IE register is used to enable/disable interrupt sources.
Bit 7 – EA: Enable All Bit
1 = Enable all interrupts
0 = Disable all interrupts
Bit 6,5 – Reserved bits
Bit 4 – ES: Enable Serial Interrupt Bit
1 = Enable serial interrupt
0 = Disable serial interrupt
Bit 3 – ET1: Enable Timer1 Interrupt Bit
1 = Enable Timer1 interrupt
0 = Disable Timer1 interrupt
Bit 2 – EX1: Enable External1 Interrupt Bit
1 = Enable External1 interrupt
0 = Disable External1 interrupt
Bit 1 – ET0: Enable Timer0 Interrupt Bit
1 = Enable Timer0 interrupt
0 = Disable Timer0 interrupt
Bit 0 – EX0: Enable External0 Interrupt Bit
1 = Enable External0 interrupt
0 = Disable External0 interrupt
Priority to the interrupt can be assigned by using interrupt priority register (IP)
Interrupt priority after Reset:
Priority | Interrupt source | Intr. bit / flag |
---|---|---|
1 | External Interrupt 0 | INT0 |
2 | Timer Interrupt 0 | TF0 |
3 | External Interrupt 1 | INT1 |
4 | Timer Interrupt 1 | TF1 |
5 | Serial interrupt | (TI/RI) |
In the table, interrupts priorities upon reset are shown. As per 8051 interrupt priorities, lowest priority interrupts are not served until microcontroller is finished with higher priority ones. In a case when two or more interrupts arrives microcontroller queues them according to priority.
IP Register: Interrupt priority register
8051 has interrupt priority register to assign priority to interrupts.
Bit 7,6,5 – Reserved bits.
Bit 4 – PS: Serial Interrupt Priority Bit
1 = Assign high priority to serial interrupt.
0 = Assign low priority to serial interrupt.
Bit 3 – PT1: Timer1 Interrupt Priority Bit
1 = Assign high priority to Timer1 interrupt.
0 = Assign low priority to Timer1 interrupt.
Bit 2 – PX1: External Interrupt 1 Priority Bit
1 = Assign high priority to External1 interrupt.
0 = Assign low priority to External1 interrupt.
Bit 1 – PT0: Timer0 Interrupt Priority Bit
1 = Assign high priority to Timer0 interrupt.
0 = Assign low priority to Timer0 interrupt.
Bit 0 – PX0: External0 Interrupt Priority Bit
1 = Assign high priority to External0 interrupt.
0 = Assign low priority to External0 interrupt.
External interrupt has two types of activation level
In 8051, two types of activation level are used. These are,
Low level triggered
Whenever a low level is detected on the INT0/INT1 pin while global and external interrupts are enabled, the controller jumps to interrupt service routine (ISR) to serve interrupt.
Falling edge triggered
Whenever falling edge is detected on the INT0/INT1 pin while global and ext. interrupts are enabled, the controller jumps to interrupt service routine (ISR) to serve interrupt.
There are lower four flag bits in TCON register required to select and monitor the external interrupt type and ISR status.
TCON: Timer/ counter Register
Bit 3- IE1:
External Interrupt 1 edge flag, set by hardware when interrupt on INT1 pin occurred and cleared by hardware when interrupt get processed.
Bit 2- IT1:
This bit selects external interrupt event type on INT1 pin,
1= sets interrupt on falling edge
0= sets interrupt on low level
Bit 1- IE0:
Interrupt0 edge flag, set by hardware when interrupt on INT0 pin occurred and cleared by hardware when an interrupt is processed.
Bit 0 - IT0:
This bit selects external interrupt event type on INT0 pin.
1= sets interrupt on falling edge
0= sets interrupt on low level
Let’s program the external interrupt of AT89C51 such that, when falling edge is detected on INT0 pin then the microcontroller will toggle the P1.0 pin.
Programming steps
/*
* 8051_External_Interrupt
*/
#include <reg51.h> /* Include x51 header file */
sbit LED = P1^0; /* set LED on port1 */
void Ext_int_Init()
{
EA = 1; /* Enable global interrupt */
EX0 = 1; /* Enable Ext. interrupt0 */
IT0 = 1; /* Select Ext. interrupt0 on falling edge */
}
void External0_ISR() interrupt 0
{
LED = ~LED; /* Toggle pin on falling edge on INT0 pin */
}
void main()
{
Ext_int_Init(); /* Call Ext. interrupt initialize */
while(1);
}
Note: For level triggered interrupt IT0 needs to be cleared i.e. IT0 = 0.